1. Field of the Invention
The present invention relates to an operation analyzing method for a semiconductor integrated circuit device, an analyzing system used in the same, and an optimization design method using the same and, more particularly, a method of applying a high-speed and high-precision operation analysis to a large-scale and high-speed driven LSI (large-scale semiconductor integrated circuit).
2. Description of the Related Art
Normally, a timing analysis is important in the design of the semiconductor integrated circuit. For example, the optimization must be achieved by executing the timing analysis to decide whether or not timings among flip-flops are matched mutually. Therefore, there is employed a method that executes an optimum design of the semiconductor integrated circuit by executing a circuit operation analysis to calculate a delay value such that the delay value is suppressed within a tolerance. However, the numbers of transistors, resistors, capacitors, etc. constituting the semiconductor integrated circuit increases steadily with the higher speed and the higher integration of the semiconductor integrated circuit. For this reason, although the circuit is designed to reduce power consumption of each circuit element, a large voltage is simultaneously consumed since the number of elements is increased. Also, a huge amount of computation is needed to execute the analysis every circuit element.
As a result, it becomes an important matter to calculate a high-precision delay value while preventing an increase in an amount of computation. Thus, various methods were proposed.
In the related art, a logic simulation applied to analyze the circuit operation is carried out by taking account of not only representative delay conditions but also power-supply voltage variation, operating temperature variation, and process variation. However, a delay variation of each element due to the operating voltage of each element in the circuit is not considered. Thus, with an increase of an integration degree, it becomes impossible to neglect an influence of such delay variation upon a delay of each element.
Therefore, there was proposed a delay calculation method that attains an improvement of reliability by calculating a voltage drop due to the power-supply wiring to consider a voltage drop of each element (See Unexamined Japanese Patent Publication No. 2000-195960).
According to this method, a power-supply voltage of each element is calculated with taking a voltage drop in the power-supply wiring of the object-of-design circuit into consideration, and then a delay value of each element is calculated by using the calculated power-supply voltage of each element.
However, according to this method, a calculation of the voltage drop is carried out, based on element voltage-drop resistance value information read out from the library that stores the voltage-drop resistance values of respective elements, and an average power-supply current value in the operation of each element. Therefore, the voltage-drop information of each element calculated herein gives average voltage information of each element in the circuit.
More particularly, as shown in FIG. 56, a voltage analyzing means 2002 executes a voltage analysis based on the average power-supply current in the operation of each element from circuit information 2001 to calculate an average voltage-drop value 2003, then a delay calculating means 2005 picks up a delay value based on the resultant average voltage-drop value by referring to a library 2004 and then outputs the delay value formed in a standard delay format (SDF: Standard Delay Format established by the nonprofit organization in USA, Silicon Integration Initiative, to represent the delay time) 2006, then a timing analyzing means 2007 executes a timing analysis by using the delay value and then outputs the result analyzed by the timing analyzing means as a timing report 2008, and then an optimizing means 2009 executes a change of design based on this analyzed result to optimize the timing.
Here, the library 2004 includes a cell library 2013 for storing delay value information every cell, and a macro library 2023 for storing delay value information every so-called macro that an assembly of cells is regarded as one lump. Then, an average voltage drop is calculated based on an average power-supply current in operation of the representative cell from cell information 2011, then this calculated value is abstracted (characterized), and then this characterized value is stored in the cell library 2013. In contrast, an average voltage drop is calculated based on an average power-supply current in operation of the representative macro from macro information 2021, then this calculated value is characterized, and then this characterized value is stored in the macro library 2023.
Also, in order to implement the logic simulation in which an influence of a voltage variation at the time of switching a logic cell upon the delay time is considered, a method of simulating the delay time based on a voltage at a power-supply terminal of a logic gate was proposed (See Unexamined Japanese Patent Publication No. HEI-7-239865).
However, in this method, the simulation is carried out based on a mean value over an execution time of a test pattern of the simulated circuit.
In addition, a method of calculating circuit element delay information in response to time-series voltage variation information during the simulation that takes account of the voltage variation was proposed (See Unexamined Japanese Patent Publication No. 2000-194732).
In the actual circuit operation in above Patent Literature 1, the voltage is varied during when the cell (instance) is operated. In contrast, in this method, since the average voltage-drop value is used to calculate the delay value, a calculation of the delay value at an impossible timing is caused and therefore a practical timing analysis for such calculation of the delay value is desired.
Also, in Patent Literatures 2 and 3, a time-series voltage is considered to calculate the delay value, nevertheless the voltage variation caused when the instance is operated is not considered.
However, in the actual circuit operation, the voltage variation during the operation becomes a big problem.
The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor integrated circuit capable of operating with high precision and having an excellent performance characteristic by taking account of a dynamic voltage drop.
Also, it is another object of the present invention to implement a high-precision and highly reliable timing verification by taking account of a dynamic voltage drop.